This invention is related to methods for making a large number of identical integrated circuits in a single semiconductor wafer, and more particularly to such wafers having one or more separate test circuits therein that may be probed and electrically analyzed for determining the efficacy of the prior diffusion, metallization and other steps and to predict the ultimate yield after the parts are broken apart, terminated and packaged.
Methods for making integrated circuits include a great many sequential steps wherein a subsequence of masking followed by impurity doping is repeated typically from 5 to 15 times depending upon the particular structures being formed. Such a subsequence includes preparing artwork, photographically reducing the art work in the form of a transparency or photographic mask, further optically reducing the image of the photographic mask in a step for exposing to light a portion of a film of photo-lithographic resist that overlies the oxidized major surface of the silicon wafer, selectively etching away only regions of the resist that were not exposed to light, selectively etching away the oxide layer through the holes made in the resist to form a silicon oxide mask having the pattern of the artwork, removing the remainder of the resist and then by diffusing from a hot gaseous atmosphere or by ion implanting, impurities are driven through the holes in the oxide mask into the silicon surface to make a particular element of the electrical components being formed there. To make another element of the electrical components the subsequence is repeated beginning with preparing a different artwork pattern and usually ending with the diffusion of a different impurity. A similar subsequence of steps ends with selectively metallizing to interconnect the integrated circuit elements.
For making a large number of identical integrated circuits in a single silicon wafer, each of the steps in the above noted sequence is performed simultaneously for forming all of the corresponding electrical component elements in all of the large number of integrated circuits, except for the one step of illumination exposure of the resist layer. The aptly named "step-and-repeat" exposure method is used whereby a pattern of illumination, corresponding to the art work, is sequentially directed to the resist film portions overlying the first, then the second and each in turn of the large number of integrated circuits to be formed in the wafer.
It is known to provide a special integrated test circuit, several of which are substituted for ones of the large number of principal integrated circuits in the wafer. This permits testing of individual integrated circuit components such as a transistor, a resistor, etc., in the test circuit. Here the components are made accessible unlike in a principal integrated circuit that is interconnected so the components are either inaccessible or electrically shunted. Each of the bulk process steps such as oxidizing, etching, diffusing, implanting and metallizing affects the entire wafer; namely all of the integrated circuits of the wafer are affected at the same time. However, because the effect on integrated circuits in one wafer region may be slightly different than in another, the above noted several test circuits are scattered about so each represents one region, and thus lack of uniformity in the processes effects are detectable as well as are the bulk or over-all effects common to all of the integrated circuits on the wafer that can be determined from measurements on the several test circuits.
However, it is not unusual in integrated circuits manufacturing that many of the defective integrated circuits are attributable to misregistration of one or more of the oxide masks. During a step and repeat illumination of sequential ones of the integrated circuits, the physical position of the illumination pattern at any particular integrated circuit must be closely aligned with the position of all prior illumination patterns. Such successive illumination pattern alignment, or lack of it, depend upon factors that commonly pertain to an individual integrated circuit and not to a group in a region of the wafer or to the whole wafer.
The above noted several test circuits that are substituted for certain of the principal integrated circuits in a wafer do not provide detection or prediction of defects in the principle integrated circuits that result from mask misregistration.
It is a primary object of this invention to provide a means for testing at the wafer level, which, how and how many integrated circuits may be defective due to mask misregistrations as well as to bulk process step variables.